Electric Circuit Analysis Johnny

321 F. Supp. at 1285. In Adams the Court found nonobvious the invention of a nonrechargeable electrical battery. The battery operated on an open circuit, became heated in normal use, and was water activated. In finding the invention non-obvious, the Court relied upon, inter alia, the following two factors: (1) a person reasonably skilled in the art would have believed that a battery which continued to operate on an open circuit and which heated in normal use was not practical [Adams' battery was practical]; and (2) a person reasonably skilled in the art would have believed that water-activated batteries were successful only when combined with non-magnesium electrolytes [one of the electrolytes in Adams' battery contained magnesium]. 383 U.S. at 51-52, 86 S. Ct. 684, 15 L. Ed. 2d 545. See also Shaw v. E.B. & A.C. Whiting Co., 417 F.2d 1097, 1104 (2d Cir. 1969), cert. denied, 397 U.S. 1076, 90 S. Ct. 1518, 25 L. Ed. 2d 811 (1970) (Justices Black. Douglas, and White dissenting)

Electric Circuit Analysis Johnny

Loren W. Linholm received the B.S. degree in Electrical Engineering from the University ofCalifornia, Berkeley, in 1968, and the M. S. degree in ElectricalEngineering from the University of Maryland, College Park,Maryland, in 1973. He has been employed by the Naval MissileCenter, Point Mugu, California, and the Department of Defense,Ft. Meade, Maryland, and since 1978, the SemiconductorElectronics Division, National Institute of Standards andTechnology, Gaithersburg, Maryland. He heads the IntegratedCircuits Technology Group, which is responsible for designing,developing, and evaluating measurements methods for evaluatingsilicon integrated circuits, manufacturing tools, and processeswith emphasis on test structures, associated data analysistechniques, novel sensors, and advanced microelectromechanicalsystems. Mr. Linholm is a member of the IEEE Electron DevicesSociety and a co-founder of the International Conference onMicroelectronic Test Structures.

Katsuhiko Kubota received theB.S. degree from Shizuoka University and the M.S. degree from theUniversity of Tokyo, in 1977 and 1979, respectively. Since hejoined Hitachi Ltd. in 1979, he has been involved in thedevelopment and reliability study of various LSIs such as DRAM,SRAM, non-volatile memory, high-speed logic, ferroelectric, andanti-fuse FPGA. From 1983 to 1984, he was a visiting researcherat Cornell University where he studied SOI. He is now responsiblefor reliability modeling and analysis of deep submicron devicescovering oxide integrity, hot carrier, electromigration and ESD.Currently he is interested in oxide leak mechanisms.

This paper reports on the use of microelectronic test structures to characterise a novel fabrication technique for thin-film electronic circuit boards. In this technology circuit tracks are formed on paper-like substrates by depositing films of a metal-loaded ink via a standard lithographic printing process. Sheet resistance and linewidth are electrically evaluated and these compared with optical and surface profiling measurements.

This paper presents a statistical analysis of a 0.18mm CMOS technology by means of efficient parameter extraction techniques applied to MOS Model 9 which allow all model parameters to be obtained from only 50 measurements. The statistical analysis demonstrates that both parameter spreads and correlations can be considered during circuit simulation.

In a Multichip Module technology (MCM) a silicon chip is used as a substrate on which other commercial chips are flipped and soldered by a screen-printing method. This complex technology has specific test problems. In this paper we present a set of classic and novel test structures addressed to the full characterization of a MCM, flip-chip, ball grid array, silicon substrate technology. We specially focus on the measurement of the ball chip to chip contact resistance, and on the electrical influence of near chips, placed on top of circuits on the substrate.

Interconnect process parameters of a 0.35mm process were fully characterized with large numbers of electrical measurements. The characterized parameters were then used with a TCAD tool to calculate capacitances of complicated test structures that mimic signal nets in real designs. The excellent agreement between calculation results and electrical measurements of the structures demonstrates that combination of TCAD tool and fully characterized interconnect process parameters can provide accurate prediction of interconnect circuit performance.